The present invention relates generally to network processors and specifically to network processors that are field programmable.
Network processors, the engines that control and route Internet traffic must constantly evolve to meet increasing performance demands, provide new functions and support new hardware and software interfaces. The amount of time available to design and produce these processor chips is shrinking in order to meet today""s time to market demands. These network processors are designed primarily using one of two methods:
1. A general purpose network processor (NP) chip produced in volume by the NP manufacturer, sold to multiple customers and customized with software to implement customer-specific functions.
2. Application specific integrated circuit (ASIC) chips where customer-specific functions are implemented in hardware and produced in smaller volumes for a single customer.
There are advantages and disadvantages to both of these approaches. The general purpose network processor is generally more cost-effective than the ASIC solution because a single part number can be produced in large quantities and be purchased for a lower cost than a low-volume custom chip solution and can also provide faster time to market because customer-specific functions are coded in software, not implemented in hardware. The disadvantage is that the customer-specific functions are limited to the performance achievable with software, which may be significantly slower than if the function were implemented in silicon.
The primary advantage of the custom ASIC solution is performance because the hardware is optimized to each customer""s function. The obvious drawback is the cost and time-to-market associated with developing customer-specific hardware.
In both the general purpose NP chip and ASIC implementations, the chip designer must decide on exactly what functions and input/output (I/O) interfaces will be supported before committing the design to silicon. Changes required to support changing I/O standards or fix errors found in high-risk logic result in costly hardware respins and potential loss of market.
What is needed is the ability to combine the flexible features on the programmable general purpose processor with the ability to adapt that hardware in the field to customer-specific functions, implement bug fixes and respond to changing I/O interface standards.
The present invention addresses such a need.
A network processor is disclosed. The network processor comprises a plurality of standard cells; and at least one field programmable gate array (FPGA) cell that can communicate with at least one of the standard cells. The at least one FPGA cell can provide a specified function based upon field programming techniques to allow for customization of the network processor.
Utilizing a method and system in accordance with the present invention, a network processor can be customized to implement a variety of functions in hardware using embedded FPGA macros. The combined technology of ASIC standard cells plus FPGA cells enables fast time-to-market for new designs while optimizing cost and performance. In addition, the combined ASIC plus FPGA on a single die allows the chip developer to use proven standard cell macros for common logic and programmable cells for high-risk logic. Through a system and method in accordance with the present invention a business process is also provided whereby an ASIC customer can either submit a custom logic file to a vendor or choose from a library of functions to program into the FPGA portion of the chip.